1. Field
Circuit design for a crystal oscillator using low-voltage transistors.
2. Background
A current trend of microelectronics design is the reduction of device sizes. As the device sizes shrink, the thickness of gate oxide in these devices also shrinks. Thus, transistors fabricated by advanced processes (e.g., submicron processes) typically withstand lower gate-source (GS) or gate-drain (GD) voltages than conventional transistors. In a high voltage environment, these low-voltage transistors often suffer failures due to oxide-overstress. However, a low-voltage transistor may sometimes need to interface with high-voltage circuits. Signals received from the high-voltage interface may cause oxide overstress in the low-voltage transistors.
For example, in a network processor chip, an on-die oscillator circuit comprising low-voltage (e.g., 2.5 V) transistors may be connected to an off-die quartz crystal that operates at a high voltage (e.g., 3.3 V). The 3.3V signal input to the crystal oscillator circuit may overstress the gate oxide and damage the crystal oscillator circuit.